Reduction of Power Dissipation in Logic Circuits
نویسندگان
چکیده
منابع مشابه
Reduction of Power Dissipation in Logic Circuits
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits...
متن کاملReduction of Power Dissipation in Logic Circuits
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today‟s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits ...
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With the advent of deep submicron technology, the number of transistors in a chip has increased very rapidly. As the complexity of VLSI circuits increases fast, the automation of the VLSI design has become very crucial not only to reduce design time and cost, but also to improve design quality. There are several criteria to measure design quality: area, delay, testability and power consumption....
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This paper proposes a method to reduce static power consumption in Adiabatic logic circuits based on Complementary Pass transistor Adiabatic Logic (CPAL) operated by two phase power clocks. We are applying power gating MTCMOS technique to reduce static power consumption in CPAL circuits. We tested MTCMOS power gating technique on 4-bit ripple carry adder to observe effect of static power reduct...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2011
ISSN: 0975-8887
DOI: 10.5120/2962-3946